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en2340qi 4a voltage mode synchronous buck pwm dc-dc converter with integrated inductor powersoc www.enpirion.com description the en2340qi is a power system on a chip (powersoc) dc-dc converter. it integrates mosfet switches, small-signal control circuits, compensation and an integrated inductor in an advanced 8x11x3mm qfn module. it offers high efficiency, excellent line and load regulation over temperature and up to the full 4a load range. the en2340qi operates over a wide input voltage range and is specifically designed to meet the precise voltage and fast transient requirements of high-performance products. the en2340 features frequency synchronization to an external clock, power ok output voltage monitor, programmable soft-start along with thermal and over current protection. the device?s advanced circuit design, ultra high switching frequency and proprietary integrated inductor technology delivers high-quality, ultra compact, non-isolated dc-dc conversion. the enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. in addition, overall system level reliability is improved gi ven the small number of components required with the enpirion solution. all enpirion products are rohs compliant and lead- free manufacturing environment compatible. features ? integrated inductor, mosfets, controller ? wide input voltage range: 4.5v ? 14v ? guaranteed 4a i out at 85c with no airflow ? frequency synchronization (external clock) ? 2% v out accuracy (over line/load/temperature) ? high efficiency (up to 95%) ? output enable pin and power ok signal ? programmable soft-start time ? pin compatible with the en2360qi (6a) ? under voltage lockout protection (uvlo) ? programmable over current protection ? thermal shutdown and short circuit protection ? rohs compliant, msl level 3, 260 o c reflow applications ? space constrained applications ? distributed power architectures ? output voltage ripple sensitive applications ? beat frequency sensitive applications ? servers, embedded computing systems, lan/san adapter cards, raid storage systems, industrial automation, test and measurement, and telecommunications figure 1. simplified applications circuit (footprint optimized) figure 2. highest efficiency in smallest solution size 50 55 60 65 70 75 80 85 90 95 100 00.511.522.533.54 efficiency (%) output current (a) efficiency vs. output current vout = 5.0v conditions v in = 8.0v avin = 3.3v dual supply actual solution size 200mm 2 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 2 ordering information part number package markings temp rating (c) package description en2340qi en2340qi -40 to +85 68-pin (8mm x 11mm x 3mm) qfn t&r en2340qi-e en2340qi qfn evaluation board packing and marking information : http://www.enpirion.com/resource-center-packing-and-marking-information.htm pin assignments (top view) nc 1 nc nc nc nc nc nc nc nc nc nc nc nc nc 2 3 4 5 6 7 8 9 pvin pvin pvin pvin pvin pvin pvin avino pg bgnd vddb s_in btmp s_out 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 69 pgnd keep out keep out figure 3: pin out diagram (top view) note a : nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to fo llow this guideline may result in part malfunction or damage. note b : shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the pcb. refer to figure 10 for details. note c : white ?dot? on top left is pin 1 indicator on top of the device package. pin description i/o legend : p=power g=ground nc=no connect i=input o=output i/o=input/output pin name i/o function 1-15, 25-26, 59, 64- 68 nc nc no connect ? these pins may be internally connected. do not connect them to each other or to any other electrical signal. failur e to follow this guideline may result in device damage. 16-24 vout o regulated converter output. connect these pins to the load and place output capacitor between these pins and pgnd pins 29-34. 27-28, 61-63 nc(sw) nc no connect ? these pins are internally connected to the common switching node of the internal mosfets. they are not to be electrica lly connected to any external signal, ground, or voltage. failure to follow this guideline may result in damage to the device. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 3 pin name i/o function 29-34 pgnd g input/output power ground. connect these pi ns to the ground electrode of the input and output filter capacitors. see vout and pvin pin descriptions for more details. 35-41 pvin p input power supply. connect to input power supply. decouple with input capacitor to pgnd pins 29-34. 42 avino o internal 3v linear regulator output. connect th is pin to avin (pin 51) for applications where operation from a single input voltage (pvin) is required. if avino is being used, place a 1f, x5r/x7r, capacitor between avino and agnd as close as possible to avino. 43 pg i/o place a 0.1f, x5r/x7r, capacitor between this pin and btmp. 44 btmp i/o see pin 43 description. 45 vddb o internal regulated voltage used for the internal control circuitry. place a 1.0f, x7r, capacitor between this pin and bgnd. 46 bgnd g see pin 45 description. 47 s_in i digital input. this pin accepts either an input clock to phase lock the internal switching frequency or a s_out signal from another en 2340qi. leave this pin floating if not used. 48 s_out o digital output. pwm signal is output on this pin. leave this pin floating if not used. 49 pok o power ok is an open drain transistor (pulled up to avin or similar voltage) used for power system state indication. pok is logic high when vout is within -10% of vout nominal. 50 enable i input enable. applying a logic high to this pin enables the output and initiates a soft-start. applying a logic low disables t he output. do not leave floating. 51 avin p 3.3v input power supply for the controller. place a 0.1f, x7r, capacitor between avin and agnd. 52, 53, 60 agnd g analog ground. this is the ground return for the controller. needs to be connected to a quiet ground. 54 vfb i/o external feedback input. the feedback loop is closed through this pin. a voltage divider at vout is used to set the output voltage. the mid- point of the divider is connected to vfb. a phase lead capacitor from this pin to vout is also required to stabilize the loop. 55 eaout o optional error amplifier output. a llows for customization of the control loop. 56 ss i/o soft-start node. the soft-start capacitor is connected between this pin and agnd. the value of this capacitor determines the startup time. 57 rclx i/o programmable over-current protec tion. placement of a resistor on this pin will adjust the over-current protection threshold. see table 2 for the recommended rclx value to set ocp at the nominal value specified in the electrical characteristics table. 58 fadj i/o adding a resistor (r fs ) to this pin will adjust the switching frequency of the en2340qi. see table 1 for suggested resistor values on r fs for various pvin/vout combinations to maximize efficiency. do not leave floating. 69 pgnd not a perimeter pin. device thermal pad to be connected to the system gnd plane for heat- sinking purposes. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 4 absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute ma ximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min max units voltages on : pvin, vout -0.5 15 v voltages on: en, pok, m/s -0.3 v in +0.3 v pvin slew rate 0.3 3 v/ms pin voltages ? avino, avin, enable, pok, s_in, s_out 2.5 6.0 v pin voltages ? vfb, ss, eaout, rclx, fadj -0.5 2.75 v storage temperature range t stg -65 150 c maximum operating junction temperature t j-abs max 150 c reflow temp, 10 sec, msl3 jedec j-std-020a 260 c esd rating (based on human body model) 2000 v esd rating (based on cdm) 500 v recommended operating conditions parameter symbol min max units input voltage range pvin 4.5 14 v avin: controller supply voltage avin 2.5 5.5 v output voltage range (note 1) v out 0.75 5 v output current i out 4 a operating ambient temperature t a -40 +85 c operating junction temperature t j -40 +125 c thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) (note 2) ja 18 c/w thermal resistance: junction to case (0 lfm) jc 2 c/w thermal shutdown t sd 160 c thermal shutdown hysteresis t sdh 35 c note 1 : rclx resistor value may need to be raised for v out > v in ? 2.5v to increase current limit threshold. note 2 : based on 2oz. external copper layers and proper thermal design in line with eij/jedec jesd51-7 standard for high thermal conductivity boards. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 5 electrical characteristics note: v in =12v, minimum and maximum values are over operating ambient temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ max units operating input voltage pvin 4.5 14.0 v controller input voltage avin 2.5 5.5 v avin under voltage lock-out rising avin uvlor voltage above which uvlo is not asserted 2.3 v avin under voltage lock-out falling avin ovlof voltage below which uvlo is asserted 2.1 v avin pin input current i avin 7 ma internal linear regulator output avino 3.3 v shut-down supply current ipvin s pvin=12v, avin=3.3v, enable=0v 500 a iavin s pvin=12v, avin=3.3v, enable=0v 50 a feedback pin voltage v fb v in = 12v, i load = 0, t a = 25c only 0.7425 0.750 0.7575 v feedback pin voltage v fb 4.5v v in 14v; 0a i load 4a 0.735 0.750 0.765 v feedback pin input leakage current i fb vfb pin input leakage current (note 3) -5 5 na v out rise time t rise c ss = 47nf (note 4 and note 5) 3.2 ms soft-start capacitor range c ss_range 10 47 68 nf maximum continuous output current i out_max_cont 4 a over current trip level i ocp reference table 2 6 a disable threshold v disable enable pin logic low 0.0 0.6 v enable threshold v enable enable pin logic high 1.8 avin v enable lockout time t enlockout 8 ms enable input current i enable 180k internal pull-down (note 3) 4 a switching frequency f sw r fs =3k ? 1.0 mhz external sync clock frequency lock range f pll_lock range of sync clock frequency 0.9 1.3 mhz s_in threshold ? low v s_in_lo s_in clock logic low level 0.8 v s_in threshold ? high v s_in_hi s_in clock logic high level 1.8 2.5 v s_out threshold ? low v s_out_lo s_out clock logic low level 0.8 v s_out threshold ? high v s_out_hi s_out clock logic high level 1.8 2.5 v pok lower threshold pok lt v out / v out_nom 90 % pok output low voltage v pokl with 4ma current sink into pok 0.4 v pok output hi voltage v pokh pvin range: 4.5v v in 14v avin v pok pin v oh leakage current (note 3) i pokl pok high 1 a note 3 : parameter not production tested but is guaranteed by design. note 4 : rise time calculation begins when avin > v uvlo and enable = high. note 5 : v out rise time accuracy does not include soft-start capacitor tolerance. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 6 typical performance curves 50 55 60 65 70 75 80 85 90 95 0 0.5 1 1.5 2 2.5 3 3.5 4 efficiency (%) output current (a) efficiency vs. output current vout = 5.0v vout = 3.3v vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v conditions v in = 12.0v avin = 3.3v dual supply 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 efficiency (%) output current (a) efficiency vs. output current vout = 5.0v vout = 3.3v vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v conditions v in = 8.0v conditions v in = 8.0v avin = 3.3v dual supply 50 55 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 2.5v vout = 1.8v vout = 1.2v vout = 1.0v conditions v in = 8.0v conditions v in = 5.0v avin = 3.3v dual supply 0.990 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output voltage (v) output current (a) output voltage vs. output current vin = 5v vin = 8v vin = 12v conditions v in = 5.0v conditions v out_nom = 1.0v 2.490 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output voltage (v) output current (a) output voltage vs. output current vin = 5v vin = 8v vin = 12v conditions v out_nom = 2.5v 3.290 3.292 3.294 3.296 3.298 3.300 3.302 3.304 3.306 3.308 3.310 0.00.51.01.52.02.53.03.54.0 output voltage (v) output current (a) output voltage vs. output current vin = 8v vin = 12v conditions v out_nom = 3.3v 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 7 typical performance curves (continued) 0.990 0.995 1.000 1.005 1.010 1.015 1.020 246810121416 output voltage (v) input voltage (v) output voltage vs. input voltage load ? = ? 0a load ? = ? 1a load ? = ? 2a load ? = ? 3a load ? = ? 4a conditions v out_nom = 1.0v 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 3.320 246810121416 output voltage (v) input voltage (v) output voltage vs. input voltage load ? = ? 0a load ? = ? 1a load ? = ? 2a load ? = ? 3a load ? = ? 4a conditions v out_nom = 3.3v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a load = 3a load = 4a conditions v in = 8v v out_nom = 1.2v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a load = 3a load = 4a conditions v in = 10v v out_nom = 1.2v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a load = 3a load = 4a conditions v in = 12v v out_nom = 1.2v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 1a load = 2a load = 3a load = 4a conditions v in = 14v v out_nom = 1.2v 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 8 typical performance characteristics vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 12v vout = 1v iout = 2a cin = 2 x 22f (1206) cout = 2 x 47 f (1206) vout (ac coupled) output ripple at 500mhz bandwidth conditions vin = 12v vout = 1v iout = 2a cin = 2 x 22f (1206) cout = 2 x 47 f (1206) vout (ac coupled) output ripple at 20mhz bandwidth conditions vin = 12v vout = 1v iout = 4a cin = 2 x 22f (1206) cout = 2 x 47 f (1206) vout (ac coupled) output ripple at 500mhz bandwidth conditions vin = 12v vout = 1v iout = 4a cin = 2 x 22f (1206) cout = 2 x 47 f (1206) enable enable startup/shutdown waveform (0a) conditions vin = 12v, vout = 1.0v, no load, css = 47nf cin = 2 x 22f (1206), cout = 2 x 47 f (1206) vout pok load enable enable startup/shutdown waveform (4a) conditions vin = 12v, vout = 1.0v, load = 4a, css = 47nf cin = 2 x 22f (1206), cout = 2 x 47 f (1206) vout pok load 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 9 typical performance characteristics (continued) vout (ac coupled) load transient from 0 to 2a conditions vin = 12v, vout = 1.2v cin = 2 x 22f (1206) cout = 2 x 47f (1206 ) load vout (ac coupled) load transient from 0 to 4a conditions vin = 12v, vout = 1.2v cin = 2 x 22f (1206) cout = 2 x 47f (1206 ) load vout (ac coupled) load transient from 0 to 2a conditions vin = 12v, vout = 2.5v cin = 2 x 22f (1206) cout = 2 x 47f (1206 ) load vout (ac coupled) load transient from 0 to 4a conditions vin = 12v, vout = 2.5v cin = 2 x 22f (1206) cout = 2 x 47f (1206 ) load 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 10 functional block diagram figure 4: functional block diagram functional description synchronous buck converter the en2340qi is a highly integrated synchronous, buck converter with integrated controller, power mosfet switches and integrated inductor. the nominal input voltage (pvin) range is 4.5v to 14v and can support up to 4a of continuous output current. the output voltage is programmed using an external resistor divider network. the control loop utilizes a type iv voltage-mode compensation network and maximizes on a low-noise pwm topology. much of the compensation circuitry is internal to the device. however, a phase lead capacitor is required along with the output voltage feedback resistor divider to complete the type iv compensation network.. the high switching frequency of the en2340qi enables the use of small size input and output capacitors, as well as a wide loop bandwidth within a small foot print. protection features: the power supply has the following protection features: ? programmable over-current protection ? thermal shutdown with hysteresis. ? under-voltage lockout protection additional features: ? switching frequency synchronization. ? programmable soft-start ? power ok output monitoring 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 11 power up sequence the en2340qi is designed to be powered by either a single input supply (pvin) or two separate supplies: one for pvin and the other for avin. single input supply application (pvin): the en2340qi has an internal linear regulator that converts pvin to 3.0v. the output of the linear regulator is provided on the avino pin. avino should be connected to avin on the en2340qi. in this application, the following external components are required: place a 1f, x5r/x7r, capacitor between avino and agnd as close as possible to avino. place a 0.1f, x5r/x7r, capacitor between avin and agnd as close as possible to avin. in addition, place a resistor (r vb ) between vddb and avin, as shown in figure 1. enpirion recommends r vb =4.75k ? . in this application, enable cannot be asserted before pvin. if no external enable signal is used, tying enable to avin meets this requirement. dual input supply application (pvin and avin): in this application, place a 0.1f, x7r, capacitor between avin and agnd as close as possible to avin. refer to figure 5 for a recommended schematic for a dual input supply application. for dual input supply applications, the sequencing of the two input supplies, pvin and avin, is very important. during power up, neither enable nor pvin should be asserted before avin. there are two common acceptable turn-on/off sequences for the device. enable can be tied to avin and come up with it, and pvin can be ramped up and down as needed. alternatively, pvin can be brought high after avin is asserted, and the device can be turned on and off by toggling the enable pin. enable operation the enable pin provides a means to enable normal operation or to shut down the device. a logic high will enable the converter into normal operation. when the enable pin is asserted (high) the device will undergo a normal soft-start. a logic low will disable the converter. a logic low will power down the device in a controlled manner and the device is subsequently shut down. the enable signal has to be low for at least the enable lockout time (8ms) in order for the device to be re- enabled. pre-bias operation the en2340qi is not designed to be turned on into a pre-biased output voltage. figure 5: dual input supply (pvin and avin) recommended schematic frequency synchronization the switching frequency of the en2340qi can be phase-locked to an external clock source to move unwanted beat frequencies out of band. the internal switching clock of the en2340qi can be phase locked to a clock signal applied to the s_in pin. an activity detector recognizes the presence of an external clock signal and automatically phase- locks the internal oscillator to this external clock. phase-lock will occur as long as the input clock frequency is in the range of 0.9mhz to 1.3mhz. when no clock is present, the device reverts to the free running frequency of the internal oscillator. adding a resistor (r fs ) to the fadj pin will adjust the frequency lower. if a 3k ? resistor is placed on fadj the nominal switching frequency of the en2340qi is 1mhz. the efficiency performance of the en2340qi for various pvin/vout combinations can be optimized by adjusting the switching frequency. table 1 shows recommended r fs values for various pvin/vout combinations in order to optimize performance of the en2340qi. pvin vout r fs 12v 5.0v 15k 3.3v 15k 2.5v 10k 1.2v 1.65k 1.0v 1.3k 5v 2.5v 22.1k 1.2v 4.87k 1.0v 3.01k table 1: recommended r fs values 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 12 spread spectrum mode the external clock frequency may be swept between 0.9mhz and 1. 3mhz at repetition rates of up to 10 khz in order to reduce emi frequency components. soft-start operation soft start is a means to ramp the output voltage gradually upon start-up. the output voltage rise time is controlled by the choice of soft-start capacitor, which is placed between the ss pin (pin 56) and the agnd pin (pin 52). rise time (ms): t r c ss [nf] x 0.067 during start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10a. typical soft-start rise time is ~3.2ms with ss capacitor value of 47nf. the rise time is measured from when v in > v uvlor and enable pin voltage crosses its logic high threshold to when v out reaches its programmed value. pok operation the pok signal is an open drain signal (requires a pull up resistor to avin or similar voltage) from the converter indicating the output voltage is within the specified range. typically, a 100k ? or lower resistance is used as the pull-up resistor. the pok signal will be logic high (avin) when the output voltage is above 90% of the programmed v out . if the output voltage goes outside of this range, the pok signal will be a logic low. over-current protection (ocp) the current limit function is achieved by sensing the current flowing through a sense pfet. when the sensed current exceeds the current limit, both power fets are turned off for the rest of the switching cycle. if the over-current condition is removed, the over-current protection circuit will re- enable pwm operation. if the over-current condition persists, the circuit will continue to protect the load. the ocp trip point is nominally set as specified in the electrical characteristics table. in the event the ocp circuit trips consistently in normal operation, the device enters a hiccup mode. while in hiccup mode, the device is disabled for a short while and restarted with a normal soft-start. the hiccup time is approximately 32ms. this cycle can continue indefinitely as long as the over current condition persists. the ocp trip point can be programmed to trip at a lower level via the rclx pin. the value of the resistor connected between rclx and ground will determine the ocp trip point. generally, the higher the rclx value, the higher the current limit threshold. note that if rclx pin is left open the output current will be unlimited and the device will not have current limit protection. reference table 2 for a list of recommended resistor values on rclx that will set the ocp trip point at the typical value of 6a, also specified in the electrical characteristics table. v out range r clx value 0.75v < v out 1.2v 31.6k ? 1.2v < v out 2.0v 33.2k ? 2.0v < v out 5.0v 36.5k ? table 2: recommended r clx values vs. v out thermal overload protection thermal shutdown circuit will disable device operation when the junction temperature exceeds approximately 150oc. after a thermal shutdown event, when the junction temperature drops by approx 20oc, the converter will re-start with a normal soft-start. input under-voltage lock-out (uvlo) internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage. hysteresis, input de- glitch and output leading edge blanking ensures high noise immunity and prevents false uvlo triggers. application information output voltage programming and loop compensation the en2340qi output voltage is programmed using a simple resistor divider network. a phase lead capacitor (c a ) plus a resistor (r ca ) are required for stabilizing the loop. figure 6 shows the required components and the equations to calculate their values. the values recommended for c a and r ca will vary with each pvin and vout combination. the en2340 solution can be optimized for either smallest size or highest performance. please see table 5 for a list of recommended c a and r ca values for each solution option. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 13 the en2340qi output voltage is determined by the voltage presented at the vfb pin. this voltage is set by way of a resistor divider between vout and agnd with the midpoint going to vfb. the en2340qi uses a type iv compensation network. most of this network is integrated. however a phase lead capacitor and a resistor are required in parallel with the upper resistor of the external feedback network (see figure 6). total compensation is optimized for either low output ripple or small solution size, and will result in a wide loop bandwidth and excellent load transient performance for most applications. see table 5 for compensation values for both options based on input and output voltage conditions. in some cases modifications to the compensation may be required. the en2340qi provides the capability to modify the control loop response to allow for customization for specific applications. for more information, contact enpirion applications engineering support (techsupport@enpirion.com). figure 6: v out resistor divider & compensation components. ra equation is only valid for low v out ripple option. for small solution size, see table 5. input capacitor selection the en2340qi requires a 22f/1206 input capacitor. low-cost, low-esr ceramic capacitors should be used as input capacitors for this converter. the dielectric must be x5r or x7r rated. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. in some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. table 3 contains a list of recommended input capacitors. recommended input capacitors description mfg p/n 22f, 16v, x5r, 10%, 1206 murata grm31cr61c226me15 22f, 16v, x5r, 20%, 1206 taiyo yuden emk316abj226ml-t table 3: recommended input capacitors output capacitor selection as seen from table 5, the en2340qi has been optimized for use with either two 47f/1206 or two 22f/0805 output capacitors. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. table 4 contains a list of recommended output capacitors output ripple voltage is determined by the aggregate output capacitor impedance. capacitor impedance, denoted as z, is comprised of capacitive reactance, effective series resistance, esr, and effective series inductance, esl reactance. placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. n total zzzz 1 ... 111 21 +++= recommended output capacitors description mfg p/n 47f, 6.3v, x5r, 20%, 1206 murata GRM31CR60J476ME19L 47f, 10v, x5r, 20%, 1206 taiyo yuden lmk316bj476ml-t 22f, 10v, x5r, 20%, 0805 panasonic ecj-2fb1a226m 22f, 10v, x5r, 20%, 0805 taiyo yuden lmk212bj226mg-t table 4: recommended output capacitors ? ? ? ? ? ? ? ? ? = = nominal 0.75v is )( value. calculated the n higher tha value standard closest toup r round )kin (r 180 a a fb fb out afb b a v vv rv r vout r 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 14 low v out ripple smallest solution size c in = 1 x 22f/1206 c out = 2 x 47f/1206 r a = 180/(vout 0.5 ) k ? c in = 1 x 22f/1206 c out = 2 x 22f/0805 pvin v out c a (pf) r ca (k ? ) nominal ripple (mv) nominal deviation (mv) (note 6) r a (k ? ) c a (pf) r ca (k ? ) nominal ripple (mv) nominal deviation (mv) (note 6) 14v ? 1.0v 10 30 ? 5 ? 47 75 27 0.1 ? 10 ? 34 1.2v 12 27 6 48 43 39 0.1 13 33 1.5v 15 27 5 53 56 39 0.1 15 38 1.8v 22 27 6 54 56 39 0.1 18 41 2.5v 27 24 8 55 51 39 0.1 26 59 3.3v 39 18 11 63 51 33 0.1 35 63 5.0v 47 8.2 18 97 75 22 5.1 42 115 12v ? 1.0v 18 22 ? 4 ? 48 27 47 0.1 ? 10 ? 35 1.2v 22 22 5 49 75 47 0.1 13 37 1.5v 27 20 5 53 75 47 0.1 15 38 1.8v 33 20 6 54 75 47 0.1 17 44 2.5v 47 18 7 54 56 47 0.1 25 59 3.3v 56 15 10 66 51 39 0.1 32 63 5.0v 56 10 16 99 75 22 5.1 39 128 10v ? 1.0v 33 18 ? 3 ? 45 27 82 0.1 ? 9 ? 35 1.2v 39 18 4 46 30 100 0.1 13 39 1.5v 47 18 5 54 30 100 0.1 14 43 1.8v 56 16 6 56 30 100 0.1 17 50 2.5v 68 12 7 57 75 56 0.1 26 70 3.3v 82 10 9 68 56 47 0.1 30 83 5.0v 100 4.3 14 98 75 33 5.1 33 140 8.0v ? 1.0v 100 8.2 ? 3 ? 51 100 100 0.1 ? 10 ? 41 1.2v 100 8.2 4 51 100 100 0.1 12 43 1.5v 100 8.2 4 54 100 100 0.1 14 46 1.8v 100 8.2 5 57 100 100 0.1 16 53 2.5v 100 8.2 6 64 91 82 0.1 23 71 3.3v 100 8.2 8 70 75 56 0.1 25 85 5.0v 100 8.2 10 110 75 56 5.1 30 127 6.6v ? 1.0v 100 8.2 ? 3 ? 60 100 100 0.1 ? 9 ? 46 1.2v 100 8.2 4 63 100 100 0.1 12 51 1.5v 100 8.2 4 65 100 100 0.1 14 56 1.8v 100 8.2 5 68 100 100 0.1 16 61 2.5v 100 8.2 5 75 100 100 0.1 19 83 3.3v 100 8.2 6 85 91 82 0.1 22 106 5v ? 1.0v 100 8.2 ? 3 ? 73 100 100 0.1 ? 9 ? 56 1.2v 100 8.2 3 75 100 100 0.1 11 63 1.5v 100 8.2 4 76 100 100 0.1 13 70 1.8v 100 8.2 4 80 100 100 0.1 13 78 2.5v 100 8.2 4 88 100 100 0.1 14 98 table 5: r a , c a , and r ca values for various pvin/vout combinations: low v out ripple vs. smallest solution size. see figure 6. use the equations in figure 6 to calculate r a (for low v out ripple option) and r b . note 6 : nominal deviation is for a 2a load transient step. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 15 thermal considerations thermal considerations are important power supply design facts that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. the enpirion powersoc helps alleviate some of those concerns. the enpirion en2340qi dc-dc converter is packaged in an 8x11x3mm 68-pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb) to act as a heat sink. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long-term reliability. the device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150c. the en2340qi is guaranteed to support the full 4a output current up to 85c ambient temperature. the following example and calculations illustrate the thermal performance of the en2340qi. example: v in = 12v v out = 3.3v i out = 4a first calculate the output power. p out = 3.3v x 4a = 13.2w next, determine the input power based on the efficiency ( ) shown in figure 7. figure 7: efficiency vs. output current for v in = 12v, v out = 3.3v at 4a, 90% = p out / p in = 90% = 0.9 p in = p out / p in 13.2w / 0.9 14.67w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 14.67w ? 13.2w 1.47w with the power dissipation known, the temperature rise in the device may be estimated based on the theta ja value ( ja ). the ja parameter estimates how much the temperature will rise in the device for every watt of power dissipation. the en2340qi has a ja value of 18 oc/w without airflow. determine the change in temperature ( t) based on p d and ja . t = p d x ja t 1.47w x 18c/w = 26.46c 27c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + t t j 25c + 27c 52c the maximum operating junction temperature (t jmax ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated. t amax = t jmax ? p d x ja 125c ? 27c 98c the maximum ambient temperature the device can reach is 98c given the input and output conditions. note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 3.5 4 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v conditions v in = 12.0v 90% 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 16 engineering schematic figure 8: engineering schematic with engineering notes 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 17 layout recommendation figure 9: top layer layout with critical components (top view). see figure 8 for corresponding schematic. this layout only shows the critical components and top layer traces for minimum footprint in single- supply mode with enable tied to avin. alternate circuit configurations & other low-power pins need to be connected and routed according to customer application. please see the gerber files at www.enpirion.com for details on all layers. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en2340qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en2340qi should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: the pgnd connections for the input and output capacitors on layer 1 need to have a slit between them in order to provide some separation between input and output current loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. recommendation 4 : the thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. the drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. recommendation 5 : multiple small vias (the same size as the thermal vias discussed in recommendation 4) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias along the edge of the gnd copper closest to the +v copper. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. if vias cannot be placed under the capacitors, then place them on both sides of the slit in the top layer pgnd copper. recommendation 6 : avin is the power supply for the small-signal control circuits. it should be connected to the input voltage at a quiet point. in figure 9 this connection is made at the input capacitor. recommendation 7 : the layer 1 metal under the device must not be more than shown in figure 9. refer to the section regarding exposed metal on bottom of package. as with any switch-mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 8: the v out sense point should be just after the last output filter capacitor. keep the sense trace short in order to avoid noise coupling into the node. contact enpirion technical support for any remote sensing applications. recommendation 9 : keep r a , c a , r b , and r ca close to the vfb pin (refer to figure 9). the vfb pin is a high-impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the agnd pins 52 and 53 instead of going through the gnd plane. recommendation 10 : follow all the layout recommendations as close as possible to optimize performance. enpirion provides schematic and layout reviews for all customer designs. contact enpirion applications engineering for detailed support (techsupport@enpirion.com). 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 18 design considerations for lead-frame based modules exposed metal on bottom of package lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package, as shown in figure 10. only the thermal pad and the perimeter pads are to be mec hanically or electrically connected to the pc board. the pcb top layer under the en2340qi should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. the ?shaded-out? area in figure 10 represents the area that should be clear of any metal on the top layer of the pcb. any layer 1 metal under the shaded-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. the solder stencil aperture should be smaller than the pc b ground pad. this will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. please consult the enpirion manufacturing application note for more details and recommendations. figure 10: lead-frame exposed metal (bottom view) shaded area highlights exposed metal that is not to be me chanically or electrically connected to the pcb. 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 19 recommended pcb footprint figure 11: en2340qi pcb footprint (top view) ? 06878 april 16, 2012 rev: b
en2340qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 20 package and mechanical figure 12: en2340qi package dimensions (bottom view) packing and marking information : http://www.enpirion.com/resource-center-packing-and-marking-information.htm contact information enpirion, inc. perryville iii corporate park 53 frontage road - suite 210 hampton, nj 08827 usa phone: 1.908.894.6000 fax: 1.908.894.6090 enpirion reserves the right to make changes in circuit design and/or specif ications at any time without notice. information fur nished by enpirion is believed to be accurate and reliable. enpirion assumes no respons ibility for its use or for infringement of patents or other th ird party rights, which may result from its use. enpirion products are not authorized for us e in nuclear control systems, as critical components in life su pport systems or equipment used in hazardous environment without the ex press written authority from enpirion 06878 april 16, 2012 rev: b

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